The reduction in DRAM memory cell refresh times at high integration densities is frequently caused by, among other things, parasitic short-channel induced charge leakage from the cell's storage capacitor. To address this reduction, attempts have been made to implant plug ions into the cell's contact regions to reduce leakage currents. A method according to one such attempt is illustrated by FIGS. 1-6. In particular, FIG. 1 illustrates a semiconductor substrate 11 having a cell array region and a peripheral circuit region. The cell array region is defined by a field oxide isolation region 12. This conventional method includes the steps of forming a blanket gate oxide film (not shown) on a face of the substrate 11. A conductive layer and insulating layer are then deposited and patterned to form insulated electrodes 14 having insulating caps 15 thereon. Next, lightly doped N-type regions 17 are formed by implanting N-type dopants into the substrate 11.
Referring now to FIG. 2, a blanket insulating film 19 is then deposited on the substrate 11. Then, a photoresist layer PR1 is patterned and used as an etching mask to form contact holes 21 in the blanket insulating film 19. A plug ion implanting step is then performed to reduce leakage currents from subsequently formed electrodes of storage capacitors, by recovering the damage generating in the semiconductor substrate 11 when the contact holes 21 were formed. Based on the plug ion implanting step, second impurity regions 23 are formed. Referring now to FIG. 3, the layer of photoresist PR1 is removed and then a layer of polysilicon is deposited in the contact holes 21 and patterned to form storage electrodes 25. Using conventional techniques, a dielectric film 27 and plate electrode 29 are then formed in sequence to complete the formation of storage capacitors.
As illustrated best by FIG. 4, a second layer of photoresist is patterned to expose a portion of the peripheral circuit region where NMOS transistors are to be formed. A selective etching step is then performed to convert the exposed insulating film 19 to sidewall spacers 31 and then a self-aligned high dose implantation step is performed to form N-type source and drain regions 33. Similarly, as illustrated by FIG. 5, a third layer of photoresist is patterned to expose a portion of the peripheral circuit region where PMOS transistors are to be formed. A selective etching step is then performed to convert the exposed insulating film 19 to sidewall spacers 35. A self-aligned high dose implantation step is then performed to form P-type source and drain regions 37.
Finally, as illustrated best by FIG. 6, the third layer of photoresist is removed and then a blanket insulating film 39 is deposited. A planarization step is then performed using another insulating film 41 such as borophosphosilicate glass (BPSG). A layer of photoresist (not shown) is then patterned and used as an etching mask to form a bit line contact hole. A layer of undoped polysilicon is then deposited into the bit line contact hole and patterned to form a bit line 43. Thereafter, plug ions are implanted to reduce the contact resistance between the bit line 43 and the cell active area, and thereby form a bit line contact region 45.
Another attempt at implanting plug ions into a memory cell's contact regions to reduce leakage currents is illustrated by FIG. 19. Here, a field ion region 5 of second conductivity type is provided to improve the isolation characteristics in a substrate region 1 of first conductivity type. However, as will be understood by those skilled in the art, the inclusion of a field ion region 5 may result in the formation of parasitic electric fields at the edges of a plurality of field oxide isolation regions 3, at the boundary between the field ion region 5 and a source/storage electrode contact region 13b of a memory cell. Such parasitic electric fields typically cause an increase in leakage currents and concomitant deterioration in a memory cell's refresh characteristics. To reduce these leakage currents, impurity regions 21 have typically been formed in the field ion region 5 by implanting dopants of first conductivity type into the storage electrode contact regions 13b. These impurity regions 21 also typically remedy the adverse consequences of etching damage which may occur in the substrate 1 during the formation of a plurality of storage electrode contact holes 20. In particular, the impurity regions 21 are typically formed so as to extend through the storage electrode contact regions 13b and into the field ion region 5 so that junction leakage current at the edges of the field oxide isolation regions 3 can be reduced.
A method of forming the memory device of FIG. 19 includes the steps of forming field oxide isolation regions 3 at a face of a semiconductor substrate 1 of first conductivity type and then implanting dopants of second conductivity type into the face of the semiconductor substrate to define a field ion region 5 therein, using the field oxide isolation regions 3 as an implant mask. Here, the energy at which the field ion region dopants are implanted is preferably selected so that at least some of the dopants implanted into the field oxide isolation regions 3 actually penetrate the field oxide isolation regions and enter underlying portions of the substrate 1, as illustrated. Next, a composite of a gate oxide layer, a conductive layer (e.g., doped or undoped polycrystalline silicon) and a capping oxide layer are formed in sequence on the face of the substrate 1. This composite of layers is then patterned using conventional techniques to define a plurality of insulated gate electrodes 12. These insulated gate electrodes 12 each comprise a gate oxide 7, gate electrode 9 and oxide cap 11. Dopants of first conductivity type are then implanted into the field ion region 5, using the insulated gate electrodes 12 as an implant mask. This implanting step is preferably performed to define self-aligned source/storage electrode contact regions 13b and self-aligned drain/bit line contact regions 13a.
A blanket first electrically insulating layer 15a (e.g., first passivation layer) is then formed on the insulated gate electrodes 12 and field oxide isolation regions 3. A bit line contact hole 16 is then formed in the first electrically insulating layer 15a, to expose a bit line contact region 13a. A bit line 17 is then patterned in the bit line contact hole 16. Next, a second electrically insulating layer 19 is formed on the first electrically insulating layer 15a. Storage electrode contact holes 20 are then formed in the second and first electrically insulating layers using conventional techniques. These storage electrode contact holes are preferably defined so that central portions of the storage electrode contact regions 13b are exposed at the face. Dopants of first conductivity type are then implanted through the storage electrode contact holes to define the above-described impurity regions 21. Although not shown, a storage electrode of a storage capacitor is then patterned in the contact holes 20.
Unfortunately, although the impurity regions 21 may reduce leakage currents at the edges of the field oxide isolation regions 3, junction leakage currents at other locations may still be present. In addition, as field oxide isolation regions are reduced in thickness as integrated circuit memory devices are scaled to smaller dimensions, the electrical isolation capability of the field oxide isolation regions is reduced. To compensate for this reduction in isolation capability, the dopant concentration in the field ion region typically has to be increased and the energy at which such dopants are implanted typically has to be decreased. However, these changes in the depth and dopant concentration of the field ion region typically cause a deterioration in a memory cell's refresh characteristics.
Thus, notwithstanding the above described methods of forming memory devices such as DRAM memory devices, there continues to be a need for improved methods of forming integrated circuit memory devices having improved refresh characteristics.